NAND type flash memories have been known as electrically-rewritable semiconductor memory devices that are capable of a high degree of integration. In a NAND type flash memory, a NAND cell unit is configured by a plurality of memory cells that are connected in series such that a source diffusion layer of one memory cell is shared as a drain diffusion layer of its adjoining memory cell. Both ends of the NAND cell unit are connected to a bit line and a source line respectively through select gate transistors. Such a configuration of the NAND cell unit realizes a smaller unit cell area and a larger memory capacity than those realized in a NOR type memory.
A memory cell of a NAND type flash memory includes a charge accumulation layer (a floating gate electrode) formed above a semiconductor substrate via a tunnel insulating film, and a control gate electrode stacked above the charge accumulation layer via an inter-gate insulating film, and stores data in a nonvolatile manner according to a charge accumulation state of the floating gate electrode. For example, a memory cell of a NAND type flash memory executes binary data storage in which a high threshold voltage state with charges injected in the floating gate electrode is represented by data “0” and a low threshold voltage state with charges discharged from the floating gate electrode is represented by data “1”. Recent memory cells also store multi-value data such as four-value data, eight-value data, and so on, by subdividing the threshold voltage distributions to be written.
In recent years, as a minimum feature size becomes smaller, and miniaturization of a nonvolatile semiconductor memory device advances more, an interval between word lines or an interval between a word line and a select gate line becomes smaller and smaller. A smaller interval between word lines causes a word-line leak to occur more easily. Thus, it is necessary to check occurrence of word-line leak. It is desired that a nonvolatile semiconductor memory device that may detect a point of occurrence of such word-line leak.
However, in a conventional nonvolatile semiconductor memory device, it is necessary to provide a pad and switch dedicated for detection of word-line leak on a chip, which is an obstacle to reduction of chip area. In addition, it is necessary to perform detection on a word line basis or a block basis. This causes a time for detection to become longer.